1. Field of the Invention
The present invention is related to an over-sampling digital-to-analog converter with variable sampling frequencies. Especially, it is related to the over-sampling digital-to-analog converter with variable sampling frequencies that has data buffering circuits between digital low-pass filter and modulator.
2. Description of the Prior Art
FIG. 1 is a block diagram of the over-sampling digital-to-analog converter. After input signals passing through an expander 11 and a digital low-pass filter 12, over-sampling digital signals are generated. A modulator 13 sigma-delta modulates the over-sampling digital signals and outputs the modulated signals with less number of bits, such as one-bit digital signal. The modulated digital signals are then sent to a digital-to-analog converter 14 and converted to analog signals. A low-pass filter 15 filters out the high-frequency noise introduced from modulator 13 to produce analog output signals. Taking audio signals as an example, a sampling frequency of input signals is 48 KHz (fs=48 KHz), a 64-time over-sampling rate is adopted for producing digital signals with over-sampling frequency of 3.072 MHz (64fs=3.072 MHz). After that, the delta-sigma modulator 13 generates modulated digital signals with single bit. The modulated digital signals contain input signals that are band-limited in 20 KHz and high-frequency noise introduced from the delta-sigma modulator 13. The noise is mostly distributed in a band above 20 KHz. The modulated signals are then converted to analog signals via a digital-to-analog converter, and filtered out noise above 20 KHz by low-pass filter 15, to produce analog audio signals. The rate of the system clock (MCLK) can be 3.072 MHz (64 fs=3.072 MHz).
If the sampling frequency of the input signals is not fixed, for example, the sampling frequency of the input signals may be 48 KHz, 44.1 KHz, 36 KHz, 24 KHz, 22.05 KHz, 16 KHz, 12 KHz, 11.025 KHz, or 8 KHz, the most direct way is to change the rate of the system clock (MCLK). For instance, when the sampling frequency fs of the system input signals is 48 KHz, the clock rate of MCLK is 3.072 MHz; when the sampling frequency fs of the system input signals changes to a quarter of the original, which is 12 KHz, the rate of the system clock (MCLK) is also changed to a quarter of the original, and the value is 768 KHz. The merit of this method is that the same system can be re-used under different input signals with various sampling frequencies, all we have to do is modifying clock rate of the system. The shortcoming is that, when the operating frequencies of the delta-sigma modulator are lowered, the in-band noise will be larger. Taking audio signals as an example, the noise in the band below 20 KHz can be heard. When the sampling frequency of input signals is 48 KHz (fs=48 KHz) and the sigma-delta modulator is operated at 64fs, the delta-sigma modulator will mainly produce the noise above 20 KHz. As showing in FIG. 2(a), a curve L1 is the distribution of noise of the delta-sigma modulator; a curve L2 is the distribution of frequency of input signals. Further, when fs is equal to 16 KHz and the clock frequency is one third of the original, the main noise is distributed above 6.6 KHz (20/3 KHz=6.6 KHz). Normally the noise between 6.6 to 20 KHz can be heard by human being, like shown in FIG. 2(b), whose curve L3 is the distribution of noise of the delta-sigma modulator, and a curve L4 is the distribution of frequency of input signals.
There are three methods in prior arts to improve the shortcoming of louder noise in the condition of lower sampling frequency fs.
The first method is to rise up the over-sampling frequency. For instance, to raise over-sampling frequency up to 384 fs, the over-sampling frequency is still 3.072 MHz when fs is 8 KHz, and the amount of the noise introduced by the sigma-delta modulator within 20 KHz is still the same. Unfortunately the over-sampling frequency is too high when fs=48 KHz, and it directly increases the difficulty in designing such circuits.
The second method is to adopt sigma-delta modulator with higher order. The modulator with higher order is capable to lower down noise in low frequency band, moving the noise to higher frequency band. For example, if a modulator with higher order produces the noise mostly in the band above 120 KHz when the sampling frequency of input signals is 48 KHz, when the system clock operates at ⅙ of the original rate, which means the sampling frequency of input signals becomes 8 KHz, the noise introduced from the modulator will be still in the band above 20 KHz. Thus, even if the sampling frequency fs is lower, the noise is yet in an acceptable range. The shortcoming is that the complexity is higher to implement a modulator with higher order, resulting in a product with larger area and more power consumption.
The third method is to use control circuits, such as a central processor, so that we can set different over-sampling rate depending on variable sampling frequencies. The method is described in U.S. Pat. No. 5,313,205. When the sampling frequency is lower, the over-sampling rate will generally be higher, thus the modulator always operates beyond a certain rate. To derive from the aforesaid, the noise within 20 KHz will not be over loud by the lower operating frequency of the modulator. This method needs additional control circuits such as a central processor and results in additional costs.